StarFive VisionFive 2/Hardware

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Hardware components

TL;DR

  • The base functionalities are operational under recent (6.12.x) kernels but the more advanced ones are "hidden"
  • Operational hardware supported out-of-the-box by the mainstream kernel: GPU, USB, eMMC, SD Card slot, GPIO, both 1GbE NICs, PWMDAC (audio jack) and the UART ;
  • Hidden advanced functionalities:
    • Video out (HDMI) ;
    • Audio DSP engine ;
    • Image processing engine ;
    • Video encoder/decoder engines ;
    • JPEG engine ;
  • Old and heavily customized 6.6/5.10 patched kernels giving all of the hidden functionalities are on Github (see https://github.com/starfive-tech/linux/)

Details

The StarFive VisionFive 2 is a Single Board Computer (SBC) based on a StarFive JH7110 SoC (rv64gc subarch), an Imagination BXE-4-32 GPU and several other components detailed hereafter. It comes in variants of 2/4/8 GB of LPDDR4 memory. See the document VisionFive2_QSG.pdf for a full specification. This SBC supports TF/SD, eMMC, USB and NVMe storage devices, as well as having a 40-pin GPIO header and a 2-bit RGPIO boot device selector switch.

  • CPU:
    • Model: SiFive JH7110 SoC running at 1.5 GHz with 5 HARTs (a HART is a CPU core abstraction, i.e. an execution context containing a full set of RISC-V architectural registers that executes its program independently from other HARTs)
    • Cores (HARTs):
      • 4× U7 64-bits RISC‑V cores (RV64GC) for general usage
      • 1x S7 64-bits RISC‑V core (RV64IMAC) for monitoring (not used in Linux)
      • 1x E24 32-bits RISC‑V core (RV32IMAFCB) for low power and control/configure tasks as a coprocessor in JH7110 SoC (Not used in Linux)
    • Datasheet: u74mc_core_complex_manual_21G1.pdf
    • Notes:
  • System DRAM:
    • Model: BIWIN 2/4/8 GB LPDDR4
    • Notes:
      • Not to be confused with the on-chip SRAM memory
  • Ethernet controllers (PHY/GMAC):
    • Model/IP: 2x Motorcomm YT8531 (1 GbE) for board revision 1.3B (one YT8531 per Ethernet plug). Older boards use models YT8521C and YT8512C (100 MbE)
    • Datasheet: YT8531_xiliejieshaov0.3.pdf
    • Linux kernel support: supported at upstream
  • Power Management Integrated Controller (PMIC):
  • On-board audio DAC:
    • Model/IP: in-house PWM-DAC
    • Linux kernel support: fully supported by Linux and ALSA without out-of-tree patches but no volume control as simple Resistor-Capacitor output which is connected to the audio jack
    • The WM8960 audio HAT for the Raspberry Pi 4 can be used on the GPIO header
  • GPIO PWM (Pulse Width Modulation generator):
    • Mode/IP: in-house
    • Linux kernel support: supported with out-of-tree patches (see SDK), patches submitted at upstream but not merged as of 6.12/6.13
    • Notes:
      • The PWM generator is connected the GPIO and can be driven from /sys.
  • CAN (Controller Area Network) bus controller:
    • Model/IP: CAST CAN-CTRL
    • Linux kernel support: supported with out-of-tree patches (see SDK), patches submitted at upstream but not merged as of 6.12/6.13
    • Notes:
  • I2C bus controller:
    • Model/IP: Synopsys DesignWare I2C adapter
    • Linux kernel support: Supported at upstream
  • SPI bus controller:
    • Model/IP: Cadence Quad SPI controller
    • Linux kernel support: Supported at upstream
  • Display (HDMI out) controllers:
    • Model/IP: VeriSilicon Vivante DC8200 (display processing) + InnoSilicon HDMI transceiver
    • Linux kernel support: supported with out-of-tree patches (see SDK), patches submitted at upstream but not merged as of 6.12/6.13
    • Notes:
      • There is a TDA998X/TDA9950 IP for CEC control (according to the source/device tree code in the SDK) => datasheet
      • No complete public datasheet found but some scarse information can be found on rvspace.org
      • Some reverse engineering done see here and here
      • Vivante DC8000 is a family, no information specific to the DC-8200 model however
      • A discussion thread on SiFi forums mentions a repository on GitHub where some information on the DC8000 can be found (HiFive Premier P550/ESWin 7700X SoC)
      • ESWin 7700X SoC TRMs can be found on GitHub.
      • Some RUST code lies here with descriptions
  • On-chip GPU, DSP units and accelerators:
    • GPU:
    • Audio DSP:
      • Model/IP: Cadence Tensilica HiFi4 DSP
      • Datasheet: No public datasheet
      • Linux kernel support: supported with out-of-tree patches (see Starfive Linux kernel fork), code needs to be ported for recent kernels (last version available is for 6.6.x kernel series)
    • Vision DSP:
      • Model/IP: Cadence Tensilica Vision P6 DSP (VP6)
      • Datasheet: No public datasheet
      • Linux kernel support: supported with out-of-tree patches (see SDK)
    • JPEG processing unit (JPU):
      • Model/IP: Chips&Media CODAJ12
      • Datasheet: No public datasheet
      • Linux kernel support: supported with out-of-tree patches (see Starfive Linux kernel fork), code needs to be ported for recent kernels (last version available is for 6.6.x kernel series)
    • Video stream encoder (H.264/H.265):
      • Model/IP: Chips&Media WAVE512
      • Datasheet: No public datasheet
      • Linux kernel support: supported with out-of-tree patches (see Starfive Linux kernel fork), code needs to be ported for recent kernels (last version available is for 6.6.x kernel series)
      • Notes:
    • Video stream decoder (H.264/H.265):
      • Model/IP: Chips&Media WAVE420L
      • Datasheet: No public datasheet
      • Linux kernel support: supported with out-of-tree patches (see Starfive Linux kernel fork), code needs to be ported for recent kernels (last version available is for 6.6.x kernel series)
      • Notes:
    • Crypto-engine:
      • Model/IP: in-house
      • Linux kernel support: supported at upstream level

RISC-V ISA standard and extensions supported

Tip
For further information: Wikipedia or the offical RISC-V specifications

When identifying the RISC-V ISA standard and extensions for the target device, the following table may be useful:

Name Description
RV32I Base Integer Instruction Set - 32-bit
RV32E Base Integer Instruction Set (embedded) - 32-bit, 16 registers
RV64I Base Integer Instruction Set - 64-bit
RV128I Base Integer Instruction Set - 128-bit
Extension
M Standard Extension for Integer Multiplication and Division
A Standard Extension for Atomic Instructions
F Standard Extension for Single-Precision Floating-Point
D Standard Extension for Double-Precision Floating-Point
G Shorthand for the base and above extensions
Q Standard Extension for Quad-Precision Floating-Point
L Standard Extension for Decimal Floating-Point
C Standard Extension for Compressed Instructions
B Standard Extension for Bit Manipulation
J Standard Extension for Dynamically Translated Languages
T Standard Extension for Transactional Memory
P Standard Extension for Packed-SIMD Instructions
V Standard Extension for Vector Operations
N Standard Extension for User-Level Interrupts
H Standard Extension for Hypervisor
S Standard Extension for Supervisor-level Instructions

In the case of the VisionFive 2, the heart is the SiFive U74-MC Core Complex composed of:

  • 4x U7 cores: RV64IMAFDC (shortform: rv64gc). They support the double-float operations (ABI = lp64d) and compressed instructions and M+S+U modes
  • 1x S7 core: RV64IMAFDC supports only M+U modes
  • All of those cores have their own PMP (Physical Memory Protection) units

Additional extensions to take into account for the U7 cores:

  • zicsr: CSR (Control and Status Register) Instructions; implied by the F extension
  • Zba: address generation
  • Zbb: basic bit manipulation

This results in the following being the descriptive and shorthand flags for the VisionFive2 board respectively: rv64imafdc_zicsr_zba_zbb, rv64gc_zba_zbb

Unsupported features for the U74:

  • Virtualisation: KVM requires the H extension
  • SIMD instructions: No support for vector operations (V)
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